The present invention relates to a PLL (Phase Locked Loop) circuit and an image display device.
The PLL circuit is operated so as to obtain an oscillatory frequency acquired by multiplying the frequency of a reference input signal by N as an output signal of a voltage-controlled oscillator (hereinafter referred to as “VCO”) and match the phase of the reference input signal to that of 1/N dividing signal (N is an arbitrary positive integer) of the VCO output signal. The PLL circuit is widely used in the analog circuit/digital circuit mixed system such as digital consumer electronics products.
Referring to FIG. 5 and FIG. 6, a conventional PLL circuit will be described. FIG. 5 is a schematic diagram of the conventional PLL circuit. The conventional PLL circuit has a reference input signal input terminal 90, a pulse width setting circuit 110, a phase comparator 140, a charge pump 150, a loop filter 160, a voltage-controlled oscillator (VCO) 100 and a 1/N frequency divider 430. The pulse width setting circuit 110 has a differentiating circuit 111 and a first counter 112. The 1/N frequency divider 430 has a second counter 132 and a reset pulse generating circuit 131. The loop filter 160 is comprised of an integrating circuit (not shown) having a capacitor and a resistance. A clock CLK is supplied to the differentiating circuit, the first counter 112, the second counter 132 and the reset pulse generating circuit 131 from the VCO 100.
The conventional PLL circuit is a generating circuit of a clock for driving an image display device (such as a liquid crystal display device). A reference input signal HD is a horizontal driving signal (horizontal synchronizing signal) extracted from an image signal input to the image display device. An output pulse of the VCO 100 (hereinafter referred to as “clock”) is used as a pixel driving pulse for shifting the input image signal on a pixel-by-pixel basis in the lateral direction (to input the image signal to a shift register with a length of one horizontal period). An output pulse of the second counter 132 (output pulse of the 1/N frequency divider 430) is used as a driving pulse for shifting an image signal of one horizontal period every horizontal period in the longitudinal direction.
The operation of the differentiating circuit 11 and the first counter 112, which constitute the pulse width setting circuit 110, will be described below. The differentiating circuit 111 detects a trailing edge of the reference input signal HD input from the reference input signal input terminal 90 and generates a first differential pulse HDR having a time width of one period of the clock CLK.
The first counter 112 receives the clock CLK at its clock input terminal and the first differential pulse HDR at its reset input terminal (active in low level). The first counter 112 is reset by the first differential pulse HDR, counts the clock CLK, decodes the count value and outputs the decoded value as a first signal HSC50. The count value of the first counter 112 at the reset is defined as M (M is a positive integer). If the period of the reference input signal HD is a reference period TH, M substantially corresponds to N in the PLL's phase locked state (N is a value set arbitrarily according to the design specification. In the conventional example, N is the number of pixels for one horizontal period). The first signal HSC50 has a rising edge at the timing of the trailing edge of the reference input signal HD, and a trailing edge at a predetermined timing. When the period of the reference input signal HD is in the proximity of the reference period TH, the duty ratio of the first signal HSC50 is typically set to be about 50%.
The operation of the reset pulse generating circuit 131 and the second counter 132, which constitute the 1/N frequency divider 430, will be described below. When the reset pulse generating circuit 131 receives the count value of the second counter 132 and, if the count value corresponds to N, it outputs a reset pulse PLL50R having a time width of one period of the clock CLK. The second counter 132 receives the clock CLK at its clock input terminal and the reset pulse PLL50R at its reset input terminal (active at low level). The second counter 132 is self-reset by the reset pulse PLL50R, counts the clock CLK, decodes the count value and outputs the decoded value as a second signal PLL50. Preferably, the second counter 132 is configured so that the duty ratio of the second signal PLL50 is about 50%. The 1/N frequency divider 430 (the second counter 132) has a rising edge at the reset timing, and a trailing edge at a predetermined timing. It may be configured so that the second signal PLL50 has the trailing edge at the timing when a predetermined time has elapsed after the reset of the second counter 132.
The phase comparator 140 compares the rising edge of the first signal HSC50 (phase of the reference input signal HD) with the trailing edge of the second signal PLL50 (phase of the 1/N frequency divider 430) and outputs a phase error signal (up signal or down signal) having a time width corresponding to the phase difference.
The charge pump 150 receives the phase error signal. In the case where the input phase error signal is the up signal., the charge pump 150 passes a certain amount of charge current Iup (the control voltage Vf increases); and in the case where the input phase error signal is the down signal, the charge pump 150 passes a certain amount of discharge current Idown (the control voltage Vf decreases) to a control voltage Vf held by the capacitor of the loop filter 160. The loop filter 160 holds the control voltage Vf of the VCO 100, with high frequency components thereof being removed. The VCO 100 receives a feedback input of the control voltage Vf and oscillates at the corresponding frequency to output the clock CLK.
The second counter 132 may output a window signal WINDOW having a time width of a predetermined period before and after the trailing edge (phase comparing timing) of the second signal PLL50 (In FIG. 6, the period from W1 to W2 during which the window signal WINDOW is high level). In this case, the phase comparator 140 outputs the phase error signal within the range of the window signal WINDOW. As a result, in such a case where one horizontal synchronizing signal of the input image signal lacks (It is not that the period of the horizontal synchronizing signal is changed), the oscillating frequency of PLL can be controlled so as not to change by a predetermined value or greater.
With the configuration mentioned above, the conventional PLL circuit follows the frequency of the reference input signal HD and outputs the second signal PLL50 in synchronization with the clock CLK having a frequency of N times larger than the above frequency and the reference input signal HD. It is defined that the period of the reference input signal HD (reference period) is TH and the oscillating period of the clock CLK is TCLK (TH=N×TCLK).
Referring to FIG. 6, the operation of the conventional PLL circuit will be described in detail. FIG. 6 is a timing chart showing the operation of the conventional PLL circuit. At times of t1, t2, t5, t8, t9 and t10 in FIG. 6, the reference input signal HD is input to the reference input signal input terminal 90.
At the time t2 in FIG. 6, the trailing edge of the reference input signal HD arrives. The first counter 112 reset at the trailing edge of the reference input signal HD outputs the first signal HSC50 having the rising edge at the time t2. The second counter 132 outputs the second signal PLL50 having the trailing edge at the time t3 later than the time t2. The phase comparator 140 sends the up signal (phase error signal) to the charge pump 150 during the points of time t2 and t3. The charge current Iup is passed to the capacitor that constitutes the loop filter 160, thereby to increase the control voltage Vf. As a result, the oscillating frequency of the VCO 100 becomes larger (the period TCLK becomes shorter) and feedback is performed to match the rising edge of the first signal HSC50 to the trailing edge of the second signal PLL50.
At the time t5, the next trailing edge of the reference input signal HD arrives. The pulse width setting circuit 110 generates the first signal HSC50 having the rising edge at the time t5. The 1/N frequency divider 430 outputs the second signal PLL50 having the trailing edge at the time t4 prior to the time t5. The phase comparator 140 sends the down signal (phase error signal) to the charge pump 150 during the points of time t4 and t5. The discharge current Idown is passed to the capacitor that constitutes the loop filter 160, thereby to decrease the control voltage Vf. As a result, the oscillating frequency of the VCO 100 becomes smaller (the period TCLK becomes longer) and feedback is performed to match the rising edge of the first signal HSC50 to the trailing edge of the second signal PLL50.
In the case where the period of the reference input signal HD is stable in proximity of the reference period TH, the conventional PLL circuit can lock the period TCLK of the VCO 100 to TH/N by repeating such feedback. At this time, the count value M of the first counter 112 at the reset is substantially same as the count value N of the second counter 132 at the reset.
In a liquid crystal display, for example, an image signal for displaying an image on the screen is driven by the output clock CLK and the second signal PLL50 of the PLL circuit in which the horizontal synchronizing signal is set as the reference input signal HD. For example, in the image signal according to PAL system, a vertical synchronizing period TV for one field (period of a vertical synchronizing signal VD) is equal to 312.5 horizontal synchronizing periods TH (1 TV=312.5 TH). When the image signal of PAL system is displayed on a liquid crystal panel, it is necessary to adjust the vertical synchronizing period TV to be an integral multiples of the horizontal synchronizing period (for example, 1 TV=312×horizontal synchronizing period) by skipping the number of lines in one vertical synchronizing period (1 TV) (which is equal to the number of pulses of the horizontal synchronizing signal). This skipping processing is performed by extending the reference period TH corresponding to V compressibility of PAL system to be longer than 64 μsec as one horizontal synchronizing period of standard PAL system in a stage prior to the PLL circuit. In this case, it is required to maintain the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal by extending one horizontal synchronizing period within the vertical retrace period to be longer than the reference period TH corresponding to V compressibility of PAL system (TH is 64 μsec or more) once during one vertical synchronizing period TV (to be less than twice as long as TH). That is, the period of the horizontal synchronizing signal needs to be made discontinuous once during one vertical synchronizing period TV. Only one period of the reference input signal HD input to the PLL circuit (horizontal synchronizing signal) is extended to be longer than the reference period TH in one vertical synchronizing period TV, and other 311 periods become the reference period TH (for example, the waveform of HD in FIG. 6).
Next, when the period of the reference input signal HD is extended to be longer than the reference period TH once in the vertical synchronizing period TV and then returned to be the reference period TH, the operation of the conventional PLL circuit will be described below.
At the times t5, t8, t9 and t10 in FIG. 6, the trailing edge of the reference input signal HD arrives. During the times t5 and t8, the period of the reference input signal HD is extended to be 1.5 times as long as the reference period TH (less than twice), thereby to become the period TSKEW. During the times t8 and t9 and the times t9 and t10, the period of the reference input signal HD returns to be the reference period TH again.
While the reference input signal HD arrives about at the time t6 when its period remains to be the reference period TH, the reference input signal HD arrives at the time t8 later than the time t6 in the period TSKEW. The phase difference between the first signal HSC50 and the second signal PLL50 is expressed as the time period between the points of time t6 and t8. Nevertheless, as the window signal WINDOW shifts to the low level at the time t7 prior to the time t8, the phase comparator 140 sends the down signal (phase error signal) to the charge pump 150 during the points of time t6 and t7. At the time t8, the count value of the first counter 112 is reset from Q (>M).
Since the time t8, the period of the reference input signal HD returns to the reference period TH. However, as the response of the loop filter 160 and the VCO 100 is not so fast, it takes a considerable time to resolve the phase difference between the first signal HSC50 and the second signal PLL50 that is generated in the period TSKEW. For that reason, as in the time period between the points of time t5 and t8, the phase comparator 140 outputs the down signal during the points of time t8 and t9 and during the points of time t9 and t10. Furthermore, during the subsequent period (not shown), the up signal is output continuously by overshoot at the phase locking of the PLL circuit. In the conventional PLL circuit, when only one period of the reference input signal HD is made discontinuous, the cycle of phase comparison is repeated several tens of times until the rising edge of the first signal HSC50 and the trailing edge of the second signal PLL50 match to each other again, thereby to stabilize the control voltage Vf input to the VCO 100 (It takes several tens of horizontal synchronizing periods to stabilize the control voltage Vf). Accordingly, stability of the frequency (period) of the clock CLK output from the VCO 100 is insufficient.
Generally, extension of the horizontal synchronizing period in the period TSKEW is performed before the start of display in the vertical direction on the liquid crystal panel (vertical blanking period). Response to the discontinuity in the period of the reference input signal HD of the PLL circuit needs to be stabilized not later than the start of effective display on the liquid crystal panel (by the start of display of the available image in a first horizontal period). In the conventional PLL circuit, however, it takes a considerable time for the clock CLK output from the VCO 100 to be stabilized after one extension of the period of the reference input signal HD. For that reason, the top curl phenomenon in which an upper part of the display is distorted occurs, resulting in a substantial deterioration in image.
When the reference period of a reference input signal becomes discontinuous only once during a prescribed period and then returns to the original reference input period, a horizontal synchronizing PLL circuit disclosed in Unexamined Patent Publication No. Sho 63-215265 detects a value of a frequency divider in the PLL circuit to generate a pseudo reference input signal, thereby to compensate the reference input signal. However, the PLL circuit has the problem that the period from the compensated signal to the next incoming reference input signal exceeds the reference period of the reference input signal. Moreover, the horizontal synchronizing PLL circuit disclosed in Unexamined Patent Publication No. Sho 63-215265 intends to improve the response stability in the vertical synchronizing period, and cannot address the stabilization of the PLL circuit in the case where only one period of the input reference input signal (HD) is extended during a predetermined period.